The present disclosure herein relates to a loop filter for a continuous time delta-sigma modulator, and more particularly, to a third order loop filter based on a single operational filter and a method of implementing a corresponding loop filter.
A continuous time delta-sigma modulator (DSM) has its own anti-aliasing characteristic and a high signal to noise ratio (SNR) characteristic. Thus, the DSM is being widely used as a data converter for efficiently implementing a wireless communication system, such as 3rd Generation Partnership Project (3GPP), Worldwide Interoperability for Microwave Access (WiMAX), etc.
With the recent development in process technology, interest in low power has increased and thus many efforts to design the DSM with low power are being made. A loop filter (LF) among blocks configuring the DSM is a block that requires greatest power consumption in design. R. Zanbaghi's 2013 JSSC paper entitled “An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT A/Modulator Dissipating 13.7 mW” and K. Matsukawa's 2010 JSSC paper entitled “A fifth order Continuous-time Delta-Sigma Modulator With Single-Opamp Resonator” have proposed DSMs that configure a multi-order LF using a single operational trans-conductance amplifier (OTA). Unlike a typical manner in which the number of integrators increases with an increase in order, the DSMs employs, as a main idea, configuring a multi-order LF through a single OTA and thus reducing the power consumption of the entire circuit. Also, a method of configuring a second order LF through a single operation amplifier has been presented in Korean Patent Application Nos. 10-2014-0015799 and 10-2014-0004103 entitled “Second order LF and multi-order delta-sigma modulator including the same” and “Delta-sigma modulator”, respectively.
In a typical art as described above, LF structures are disclosed which may reduce the power consumption and area of the DSM by the configuring of a second order LF using a single operational amplifier. However, it is difficult to find a third order filter implemented by using a single operational amplifier. The reason is that when the order of the LF is equal to or higher than a third order, it is difficult to find a circuit configuration that satisfies a third order transfer function through a connection of a resistor and a capacitor. The reason is also that a resistor value and a capacitor value changes according to a change in process used for implementing a circuit, thus it is significantly difficult to provide a stable LF.
In this situation, Matsukawa from Panasonic corporation has proposed a third order LF in A 10 MHz BW 50 fJ/conv. Continuous Time ΔΣModulator with High-order Single Opamp Integrator Using Optimization-based Design Method”, in Symposium on VLSI Circuits, 2012.
However, in order to implement the proposed circuit, correction should be performed based on simulation after all parasitic components present in the circuit and an operational amplifier have been modeled. Therefore, there are many difficulties in actually manufacturing and implementing the LF.